FPGA Design and Implementation Course

This course provides a comprehensive introduction to FPGA design and implementation, combining theoretical foundations with practical experience. Participants will learn key concepts of digital logic, FPGA architecture, and Verilog programming, progressing from basic design principles to real-world applications using the Vivado Design Suite. The course is ideal for those new to FPGA development, offering hands-on training for creating and implementing hardware designs.

Course Objectives

The course provides experience with:

• Understanding the fundamentals of digital logic, Boolean algebra, and Karnaugh maps.
• Designing combinational and sequential circuits using logic gates and flip-flops.
• Learning FPGA architecture and the design flow.
• Creating projects in Vivado Design Suite, including source file management and synthesis.
• Writing and debugging Verilog code for combinational and sequential circuits.
• Implementing designs, generating bitstreams, and testing on FPGA hardware.

Who Should Attend?

• Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite.

Learning Outcomes

After completing this training, participants will be able to:

• Use the New Project Wizard to create a new Vivado IDE project.
• Describe the supported design flows of the Vivado IDE.
• Generate a DRC report to detect and fix design issues early in the flow.
• Synthesize and implement an HDL design.

Instructor

Ron Amir, admin of the EmbeddedMaker community, is an Electrical and Computer Engineer graduate from Ben-Gurion University, with extensive industry experience.

• Worked at Intel in various roles, including developer and manager of development teams.

Course Syllabus

Session 1: Binary System and Boolean Algebra

• Binary System:
  • Binary to decimal and decimal to binary conversions.
  • Gray code: Definition and applications.
  • Conversions between binary and Gray code.
• Boolean Algebra:
  • Laws of Boolean algebra (Commutative, Associative, Distributive).
  • De Morgan’s Theorems.
  • Simplifying Boolean expressions.
• Functions Presentation:
  • Sum of Products (SOP).
  • Writing expressions from truth tables.
  • Simplifying SOP forms.
• Basic Operations and Truth Tables:
  • AND, OR, NOT operations.
  • Building truth tables for logical functions.

Session 2: Logic Gates and Circuit Optimization

• Fundamental Gates:
  • AND, OR, NOT, NAND, NOR, XOR gates.
  • Truth tables and logical operations.
• Multiple Entrance Gates:
  • Gates with multiple inputs (e.g., 3-input AND, OR gates).
  • Real-life applications of multi-input gates.
• Universal Gates:
  • NAND and NOR as universal gates.
  • Designing any logical function using only NAND or NOR.
• Karnaugh Maps (K-Maps):
  • Simplifying Boolean functions using K-Maps.
  • Optimal logic reduction for combinational circuits.
  • Handling “don’t care” conditions in K-Maps.

Exercise 1 – Binary System, Boolean Algebra, and Logic Gates

• Design a combinational logic circuit based on a given truth table.
• Use Boolean algebra and Karnaugh maps to simplify the logic expression.
• Implement the simplified logic using fundamental and universal gates.
• Construct truth tables and verify the circuit in simulation.

Session 3: Sequential Logic and Flip-Flops

• Introduction to Sequential Logic:
  • Differences between combinational and sequential logic.
  • Applications of sequential circuits.
• Flip-Flops:
  • D, T, JK, and SR flip-flops: Structure and truth tables.
  • Designing edge-triggered and level-triggered flip-flops.
  • Registers and counters using flip-flops.

Session 4: Finite State Machines (FSMs)

• Introduction to FSMs:
  • Mealy vs. Moore state machines.
  • State diagrams and state tables.
• FSM Design:
  • Defining states and transitions.
  • Designing FSMs for simple applications (e.g., sequence detectors).
• FSM Implementation:
  • Converting state diagrams to flip-flop-based circuits.

Exercise 2 – Sequential Logic and FSMs

• Design a simple sequence detector that recognizes a predefined bit pattern.
• Create the corresponding state diagram and state table.
• Implement the design using flip-flops and FSM principles in Verilog.
• Simulate the circuit to verify correct detection of the sequence.

Session 5: FPGA Architecture Overview and Design Flow

• FPGA Architecture:
  • Configurable Logic Blocks (CLBs).
  • Interconnects and routing.
  • Input/Output (I/O) blocks.
• FPGA Design Flow:
  • RTL design, synthesis, and implementation steps.
  • Overview of tools and steps for FPGA development.

Session 6: Vivado Introduction and Verilog Basics

• Vivado Design Suite:
  • Setting up a Vivado project.
  • Adding and managing source files.
  • Navigating Vivado’s interface and tools.
• Verilog Basics:
  • Module structure, syntax, and keywords.
  • Writing combinational logic in Verilog.
  • Common mistakes and debugging Verilog code.

Exercise 3 – FPGA Architecture, Design Flow, and Verilog Basics

• Implement a basic digital system, such as a binary counter or a traffic light controller, in Verilog.
• Write the Verilog module and testbench.
• Perform behavioral simulation to validate functionality.
• Synthesize the design and ensure there are no synthesis warnings/errors.

Session 7: Verilog for Sequential Circuits, Behavioral Simulation, and Synthesis

• Verilog for Sequential Circuits:
  • Using always blocks and sensitivity lists.
  • Implementing flip-flops, registers, and counters in Verilog.
• Behavioral Simulation:
  • Testing Verilog designs in Vivado.
  • Simulating and validating functionality before synthesis.
• Synthesis:
  • Translating RTL to a netlist.
  • Resolving synthesis warnings and optimizing designs.

Session 8: Implementation, Bitstream Generation, Debugging, and Optimization

• Implementation and Bitstream Generation:
  • Design Rule Checks (DRC) and resolving errors.
  • Generating a bitstream and programming the FPGA.
• Debugging and Optimization:
  • Using Vivado logic analyzer.
  • Timing constraints and power optimization techniques.

Exercise 4 – Sequential Verilog, Implementation, and Debugging

• Design a simple Arithmetic Logic Unit (ALU) with basic operations (addition, subtraction, AND, OR).
• Implement the ALU in Verilog and create a testbench to verify individual operations.
• Synthesize the design and generate a bitstream for FPGA programming.
• Debug timing and functionality issues using Vivado tools.

Session 9: ALU Project (Part 1)

• Project Introduction:
  • Design specifications for an Arithmetic Logic Unit (ALU).
  • Functional requirements: Addition, subtraction, AND, OR, etc.
• Design Phase:
  • Writing the RTL for ALU operations in Verilog.
  • Simulating individual ALU operations.

Session 10: ALU Project (Part 2)

• Integration and Testing:
  • Integrating ALU modules.
  • Verifying correct operation through simulation.
• Implementation and Optimization:
  • Synthesizing the design.
  • Implementing, debugging, and testing on FPGA hardware.

Upcoming Course Details

• Start Date: March 19th
• Time: Wednesdays, 19:30 – 21:30
• Format: Live Online Classes